Ferroelectric materials are composed of many randomly-distributed permanently polarized regions. Under the presence of an electric field, the regions with a polarization component in the direction of the electric field grow at the expense of the non-aligned regions so that a net polarization can result. If the electric field decreases, the polarization also decreases but at a slower rate so that even when the electric field becomes zero, a remnant polarization remains. This remnant polarization, existed under zero field condition (i.e., when power is turned off), is the basis of ferroelectric nonvolatile memory devices such as ferroelectric transistors.
The ferroelectric transistor is typically a ferroelectric-gate-controlled semiconductor field-effect transistor (FET), which employs a ferroelectric film in contact with a silicon substrate, and in which a proper polarization of the ferroelectric film can create an inversion layer in the silicon channel of the transistor. The basic ferroelectric-gate controlled field-effect transistor is a metal-ferroelectric silicon (MFS) FET. The term MFS represents the layers in the gate stack of the ferroelectric transistor, consisting a metal (M) gate electrode disposed on a ferroelectric (F) gate dielectric on the silicon (S) channel of the transistor.
However, effective transistor operation of the above MFS transistor is difficult to achieve due to the requirement of the ferroelectric/silicon interface. When a ferroelectric film is deposited directly on the silicon substrate, metals and oxygen from the ferroelectric layer may diffuse into the ferroelectric-silicon interface, creating interface trapped charges which affect the polarization of the ferroelectric film, and overall may make the operation of the ferroelectric transistor unstable. Further, since the thermal expansion coefficient and lattice structure of a ferroelectric film is not compatible with silicon, it is very difficult to form a high-quality ferroelectric film with a clean interface directly on the silicon substrate.
Various designs have been proposed to address the drawbacks posed by the direct ferroelectric/silicon interface such as the addition of an interface layer such as a gate dielectric, a metal layer, a conductive metal oxide or a doped conductive metal oxide between the ferroelectric film and the silicon substrate.
The gate dielectric interface design can overcome the surface interface and surface state issues of a ferroelectric layer in contact with the silicon substrate, but they incorporate other difficulties such as higher operation voltage and trapped charges in the bottom floating gate layer. The operation voltage of these transistors is higher than the ferroelectric layer programming voltage by an amount of the voltage across the gate dielectric. And when there is a voltage applied across the ferroelectric thin film, there will be current flow in the gate stack, and charges would be trapped in this floating electrode. The trapped charges may neutralize the polarization charges at the interface of the bottom electrode and the ferroelectric film and could shorten the memory retention time of this structure.
The metal interface design is based on the formation of a Schottky diode in a metal-ferroelectric-metal silicon (MFMS) device. A Schottky barrier is formed between the bottom metal electrode of the gate unit (or a very shallow junction layer) and the silicon substrate. The Schottky ferroelectric gate memory transistor requires a space between the bottom electrode and the source and drain region and a very shallow n-channel under the gate, therefore the drive current of the Schottky ferroelectric gate memory transistor can be relatively low.
Other novel ferroelectric transistor designs employ a conductive oxide, a conductive metal oxide or a doped conductive metal oxide interfacial layer between the ferroelectric material and the silicon substrate, as disclosed in co-pending application entitled “Conductive metal oxide gate ferroelectric memory transistor”, and “In2O3 thin film resistivity control by doping metal oxide insulator for MFMox device applications” of the same first inventors, hereby incorporated by reference. A conductive oxide interface layer does not have the drawbacks of a dielectric interface layer, and may not have the drawbacks of the metal interface layer of a Schottky diode formation. The conductive oxide interfacial layer may improve the quality of the ferroelectric film and the operation of the ferroelectric transistor by possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem at the ferroelectric interface to improve the reliability of the ferroelectric transistor, and possible etch selectivity improving with other dielectric and metal films.
Despite the obvious advantages of the conductive oxide, prior art ferroelectric transistor designs all employ a silicon conduction channel, leading to relatively complicated device fabrication process, together with the difficulty in 3D integration.